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数字逻辑电路分析与设计(第2版)(英文版)/国外电子与通信教材系列

  • 定价: ¥129
  • ISBN:9787121398704
  • 开 本:16开 平装
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  • 折扣:
  • 出版社:电子工业
  • 页数:609页
  • 作者:(美)Victor P.Nel...
  • 立即节省:
  • 2020-11-01 第1版
  • 2020-11-01 第1次印刷
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导语

  

内容提要

  

    本书以介绍数字设计的基础知识以及丰富实例为主要特色,并在第一版的基础上进行了全面的修订与更新,更加突出了数字设计相关技术的应用。本书的内容包括:计算机与数字系统,数制系统,逻辑电路与布尔代数,组合逻辑电路分析与设计,时序逻辑电路简介,同步时序逻辑电路分析与设计,异步时序逻辑电路分析与设计,可编程逻辑器件,数字系统设计。
    本书可作为电气工程、电子工程、通信工程和计算机工程或计算机科学等相关专业的双语教材,也可作为电子设计工程师的参考书。

目录

O  Computers and Digital Systems
  Learning Objectives
  0.1  A Brief History of Computing
    0.1.1  Beginnings:Mechanical Computers
    0.1.2  Early Electronic Computers
    0.1.3  The First Four Generations of Computers
    0.1.4  The Fifth Generation and Beyond
  0.2  Digital Systems
    0.2.1  Digital versus Analog Systems
    0.2.2  Digital System Levels of Abstraction
  0.3  Electronic Technologies
    0.3.1  Moore's"Law"
    0.3.2  Fixed versus Programmable Logic
    0.3.3  Microcontrollers
    0.3.4  Design Evolution
  0.4  Applications of Digital Systems
    0.4.1  General-Purpose Digital Computers
    0.4.2  Controllers
    0.4.3  Internet of Things (IoT)
    0.4.4  Interfacing
  0.5  Summary and Review Questions
  0.6  Collaboration Activities
    References
1  Number Systems and Digital Codes
  Learning Objectives
  1.1  Number Systems
    1.1.1  Positional and Polynomial Notations
    1.1.2  Commonly Used Number Systems
  1.2  Arithmetic
    1.2.1  Binary Arithmetic
    1.2.2  Hexadecimal Arithmetic
  1.3  Base Conversions
    1.3.1  Conversion Methods and Algorithms
    1.3.2  Conversion between Base A and Base B When B=Ak
  1.4  Signed Number Representation
    1.4.1  Sign Magnitude Numbers
    1.4.2  Complementary Number Systems
  1.5  Digital Codes
    1.5.1  Numeric Codes
    1.5.2  Character and Other Codes
    1.5.3  Error Detection and Correction Codes
  1.6  Summary and Review Questions
  1.7  Collaboration Activities
    Problems
2  Logic Circuits and Boolean Algebra
  Learning Obiectives
  2.1  Logic Gates and Logic Circuits
    2.1.1  Truth Tables
    2.1.2  Basic Logic Gates
    2.1.3  Combinational Logic Circuits
    2.1.4  Sequential Logic Circuits
  2.2  Hardware Description Languages (HDLs)
    2.2.1  Verilog
    2.2.2  VHDL
  2.3  Boolean Algebra
    2.3.1  Postulates and Fundamental Theorems
    2.3.2  Boolean(Logic)Functions and Equations
    2.3.3  Minterms,Maxterms,and Canonical Forms
    2.3.4  Incompletely Specified Functions (Don't Cares)
  2.4  Minimization of Logic Expressions
    2.4.1  Minimization Goals and Methods
    2.4.2  Karnaugh Maps(K-Maps)
    2.4.3  Minimization of Logic Expressions Using K-Maps
    2.4.4  Quine-McCluskey Method
  2.5  Summary and Review Questions
  2.6  Collaboration Activities
    Problems
3  Combinational Logic Circuit Design and Analysis
  Learning Objectives
  3.1  Design of C ombinational Logic Circuits
    3.1.1  AND-OR and NAND-NAND Circuits
    3.1.2  OR-AND and NOR-NOR Circuits
    3.1.3  Two-Level Circuits
    3.1.4  M ultilevel Circuits and Factoring
    3.1.5  EXCLUSIVE-OR(XOR)Circuits
  3.2  Analysis of Combinational Circuits
    3.2.1  Boolean Algebra
    3.2.2  Truth Tables
    3.2.3  Timing Diagrams
    3.2.4  Positive and Negative Logic
  3.3  Design Using Higher-Level Devices
    3.3.1  Decoders
    3.3.2  Encoders
    3.3.3  Multiplexers and Demultiplexers
    3.3.4  Arithmetic Circuits
  3.4  Summative Design Examples
    3.4.1  Design Flow
    3.4.2  Bank Security-Lock Controller
    3.4.3  Seven-Segment Display Decoder
    3.4.4  Four-Function Arithmetic Logic Unit (add,subtract,AND,XOR)
    3.4.5  Binary Array M ultiplier
  3.5  Sum mary and Review Questions
  3.6  Collaboration Activities
    Problems
4  Introduction to Sequential Circuits
  Learning Objectives
  4.1  M odels and Classes of Sequential Circuits
    4.1.1  Finite-State Machines
    4.1.2  State Diagrams and State Tables
    4.1.3  Algorithmic State Machines
  4.2  Memory Devices
    4.2.1  Latches
    4.2.2  Flip-Flops
    4.2.3  Latch and Flip-Flop Summary
  4.3  Registers
  4.4  Shift Registers
  4.5  Counters
    4.5.1  Synchronous Binary Counters
    4.5.2  Asynchronous Binary Counters
    4.5.3  Modulo-N Counters
    4.5.4  Ring and Twisted-Ring Counters
  4.6  Summative Design Examples
    4.6.1  Register File
    4.6.2  Multiphase Clock
    4.6.3  Digital Timer
    4.6.4  Programmable Baud Rate Generator
  4.7  Summary and Review Questions
    References
  4.8  Collaboration Activities
    Problems
5  Synchronous Sequential Logic Circuit Analysis and Design
  Learning Objectives
  5.1  Analysis of Sequential Circuits
    5.1.1  Circuit Analysis Using State Diagrams and State Tables
    5.1.2  Analysis of Sequential Circuit Logic Diagrams
    5.1.3  Summary
  5.2  Design of Synchronous Sequential Circuits
    5.2.1  Design Procedure
    5.2.2  Flip-Flop Input Tables
    5.2.3  Design Examples
    5.2.4  One-Hot Finite-State Machine Design Method
    5.2.5  Incompletely Specified Sequential Circuits
  5.3  State Reduction in Sequential Circuits
    5.3.1  Redundant States
    5.3.2  State Reduction in Completely Specified Circuits
  5.4  Summative Design Examples
    5.4.1  Drink Vending Machine Control Unit
    5.4.2  Binary Multiplier
    5.4.3  Traffic Light Controller
  5.5  Summary and Review Questions
    References
  5.6  Collaboration Activities
    Problems
6  Asynchronous Sequential Circuit Analysis and Design
  Learning Objectives
  6.1  Types of Asynchronous Circuits
  6.2  Analysis and Design of Pulse-Mode Circuits
    6.2.1  Analysis of Pulse-Mode Circuits
    6.2.2  Design of Pulse-Mode Circuits
  6.3  Analysis of Fundamental-Mode Circuits
    6.3.1  Introduction
    6.3.2  Excitation and Flow Tables
    6.3.3  Analysis Procedure
  6.4  Design of Fundamental-Mode Circuits
    6.4.1  Flow Table Design and Realization
    6.4.2  Races and Cycles
    6.4.3  Eliminating Race Conditions
    6.4.4  Hazards
  6.5  Summative Design Examples
    6.5.1  Design Flow
    6.5.2  Asynchronous Vending Machine Controller
    6.5.3  Asynchronous Bus Arbiters
  6.6  Summary and Review Questions
  6.7  Collaboration Activities
    Problems
7  Programmable Digital Logic Devices
  Learning Objectives
  7.1  Programmable Digital Logic Device Technology
  7.2  Field-Programmable Gate Arrays(FPGAs)
    7.2.1  Configurable Logic Blocks
    7.2.2  Input/Output Blocks
    7.2.3  Interconnect Resources
    7.2.4  Clock Resources
    7.2.5  Other FPGA Resources and Options
    7.2.6  FPGA Design Process and Examples
  7.3  Programmable Logic Devices(PLDs)
    7.3.1  Array Structures for Combinational Logic Functions
    7.3.2  PLD Output and Feedback Options
    7.3.3  PLDs for Sequential Circuit Applications
    7.3.4  Complex PLDs(CPLDs)
    7.3.5  Design Examples
  7.4  Summative Design Examples
    7.4.1  Binary Division Circuit
    7.4.2  M ultiplexed Seven-Segm ent Display Controller
  7.5  Summary and Review Questions
    References
  7.6  Collaboration Activities
    Problems
8  Design of Digital Systems
  Learning Objectives
  8.1  Design Processes
    8.1.1  Hierarchical D esign
    8.1.2  Fixed Logic versus Programmable Logic
    8.1.3  Digital System Design Flow
  8.2  Design Examples
    8.2.1  Tiny RISC4(TRISC4)Processor
    8.2.2  One-Lane Traffic Controller
    8.2.3  Universal Asynchronous Receiver/Transmitter (UART)
    8.2.4  Elevator Controller
  8.3  Summary and Review Questions
  8.4  Collaboration Activities
    Problems
Appendix A  Verilog Primer
  A.1  Introduction
  A.2  General Concepts and Modules
    A.2.1  Module Structure
    A.2.2  Port Declarations
    A.2.3  Data Types
    A.2.4  Numbers
  A.3  Gate-Level Structural Modeling
    A.3.1  Gate Types
    A.3.2  Gate Delays
  A.4  Dataflow Modeling
    A.4.1  Expressions,Operands,and Operators
    A.4.2  Continuous Assignment Statements
    A.4.3  Continuous Assignment Statement Delay
  A.5  Behavioral Modeling
    A.5.1  Procedural Blocks
    A.5.2  Procedural Assignments
    A.5.3  Timing Control
    A.5.4  case Statements
    A.5.5  if...else Statements
    A.5.6  Loop Statements
    A.5.7  Block Execution
  A.6  Hierarchical Modeling
    A.6.1  Functions and Tasks
    A.6.2  Structural Models
  A.7  System Tasks and Compiler Directives
  A.8  Test Benches
  A.9  Summary of Features
  References
Appendix B  VHDL Primer
  B.1  Introduction
  B.2  Design Unit Structure
    B.2.1  Signals and Data Types
    B.2.2  Operators and Expressions
    B.2.3  Design Entities
    B.2.4  Design Architectures
  B.3  Behavioral and Dataflow Models
    B.3.1  Concurrent Signal Assignments
    B.3.2  Signal Delays
    B.3.3  Conditional Signal Assignments
    B.3.4  Selected Signal Assignments
  B.4  Structural and Hierarchical Models
    B.4.1  Component Declaration
    B.4.2  Component Instantiation
  B.5  Mixed Modeling Styles
  B.6  Modeling Sequential Behavioral
    B.6.1  Process Construct
    B.6.2  Sequential Statements
    B.6.3  Sequential Circuit Models
    B.6.4  Synchronous and Asynchronous Control Signals
    B.6.5  Finite-State Machine Models
    B.6.6  Register Transfer Level(RTL)Design
  B.7  Subprograms,Packages,and Libraries
    B.7.1  Functions and Procedures
    B.7.2  Packages and Libraries
  B.8  Test Benches
  B.9  Summary of Features and Keywords
  References